View MT28F008B3WG-9B_3457147.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 8mb smart 3 boot block flash memory products and specifications discussed herein are subject to change by micron without notice. 8mb smart 3 boot block flash memory q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. general description the mt28f008b3 (x8) and mt28f800b3 (x16/x8) are low-voltage, nonvolatile, electrically block-erasable (flash), programmable memory devices containing 8,388,608 bits organized as 524,288 words (16 bits) or 1,048,576 bytes (8 bits). writing and erasing the device is done with a v pp voltage of either 3.3v or 5v, while all operations are performed with a 3.3v v cc . due to process technology advances, 5v v pp is optimal for application and production programming. these devices are fabricated with microns advanced 0.18m cmos floating-gate process. the mt28f008b3 and mt28f800b3 are organized into eleven separately erasable blocks. to ensure that critical firmware is protected from accidental erasure or overwrite, the devices feature a hardware-protected boot block. this block may be used to store code imple- mented in low-level system recovery. the remaining blocks vary in density and are written and erased with no additional security measures. refer to microns web site ( www.micron.com/flash ) for the latest data sheet. flash memory features ? eleven erase blocks: 16kb/8k-word boot block (protected) two 8kb/4k-word parameter blocks eight main memory blocks ? smart 3 technology (b3): 3.3v 0.3v v cc 3.3v 0.3v v pp application programming 5v 10% v pp application/production programming 1 ? compatible with 0.3m smart 3 device ? advanced 0.18m cmos floating-gate process ? address access time: 90ns ? 100,000 erase cycles ? industry-standard pinouts ? inputs and outputs are fully ttl-compatible ? automated write and erase algorithm ? two-cycle write/erase sequence ? tsop, sop and fbga packaging options ? byte- or word-wide read and write (mt28f800b3): 1 meg x 8/512k x 16 options marking ? timing 90ns access -9 ? configurations 1 meg x 8 mt28f008b3 512k x 16/1 meg x 8 mt28f800b3 ? boot block starting word address top (7ffffh) t bottom (00000h) b ? operating temperature range commercial (0oc to +70oc) none extended (-40oc to +85oc) et ? packages 40-pin tsop type i (mt28f008b3) vg 48-pin tsop type i ( mt28f800b3) wg 44-pin sop ( mt28f800b3) sg note: 1. this generation of devices does not support 12v v pp production programming; however, 5v v pp application production programming can be used with no loss of performance. part number example: mt28f800b3wg-9 bet mt28f008b3 mt28f800b3 3v only, dual supply (smart 3) 40-pin tsop type i 48-pin tsop type i 44-pin sop
2 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory pin assignment (top view) a16 a15 a14 a13 a12 a11 a9 a8 we# rp# v pp wp# a18 a7 a6 a5 a4 a3 a2 a1 a17 v ss nc a19 a10 dq7 dq6 dq5 dq4 v cc v cc nc dq3 dq2 dq1 dq0 oe# v ss ce# a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40-pin tsop type i a15 a14 a13 a12 a11 a10 a9 a8 nc nc we# rp# v pp wp# nc a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte# v ss dq15/(a - 1) dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v pp a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce# v ss oe# dq0 dq8 dq1 dq9 dq2 dq10 dq3 dq11 rp# we# a8 a9 a10 a11 a12 a13 a14 a15 a16 byte# v ss dq15/(a - 1) dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 48-pin tsop type i 44-pin sop order number and part marking mt28f800b3sg-9 b mt28f800b3sg-9 t mt28f800b3sg-9 bet mt28f800b3sg-9 tet order number and part marking mt28f800b3wg-9 b mt28f800b3wg-9 t mt28f800b3wg-9 bet mt28f800b3wg-9 tet order number and part marking mt28f008b3vg-9 b mt28f008b3vg-9 t mt28f008b3vg-9 bet mt28f008b3vg-9 tet
3 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory functional block diagram 16kb boot block 8kb parameter block 8kb parameter block 96kb main block 128kb main block 128kb main block y - select gates sense amplifiers write/erase-bit compare and verify addr. buffer/ latch power (current) control addr. counter command execution logic i/o control logic v pp switch/ pump status register identification register y - decoder 128kb main block x - decoder/block erase control output buffer input buffer state machine byte# 2 a0Ca18/(a19) ce# oe# we# rp# v pp dq15/(a - 1) 2 mux dq15 8 8 7 dq8Cdq14 2 dq0Cdq7 16 8 19 (20) 7 a-1 9 (10) 10 8 output buffer output buffer input buffer input buffer input data latch/mux 7 a9 v cc wp# 1 128kb main block 128kb main block 128kb main block 128kb main block note: 1. does not apply to mt28f800b3sg. 2. does not apply to mt28f008b3.
4 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory pin descriptions 44-pin sop 40-pin tsop 48-pin tsop numbers numbers numbers symbol type description 43 9 11 we# input write enable: determines if a given cycle is a write cycle. if we# is low, the cycle is either a write to the command execution logic (cel) or to the memory array. C 12 14 wp# input write protect: unlocks the boot block when high if v pp = v pph 1 (3.3v) or v pph 2 (5v) and rp# = v ih during a write or erase. does not affect write or erase operation on other blocks. 12 22 26 ce# input chip enable: activates the device when low. when ce# is high, the device is disabled and goes into standby power mode. 44 10 12 rp# input reset/power-down: when low, rp# clears the status register, sets the internal state machine (ism) to the array read mode and places the device in deep power-down mode. all inputs, including ce#, are dont care, and all outputs are high-z. rp# unlocks the boot block and overrides the condition of wp# when at v hh (12v), and must be held at v ih during all other modes of operation. 14 24 28 oe# input output enable: enables data output buffers when low. when oe# is high, the output buffers are disabled. 33 C 47 byte# input byte enable: if byte# = high, the upper byte is active through dq8Cdq15. if byte# = low, dq8Cdq14 are high-z, and all data is accessed through dq0Cdq7. dq15/(a - 1) becomes the least significant address input. 11, 10, 9, 8, 21, 20, 19, 18, 25, 24, 23, a0Ca18/ input address inputs: select a unique 16-bit word or 8-bit byte. the 7, 6, 5, 4, 42, 17, 16, 15, 14, 22, 21, 20, (a19) dq15/(a - 1) input becomes the lowest order address when 41, 40, 39, 8, 7, 36, 6, 5, 19, 18, 8, 7, byte# = low (mt28f800b3) to allow for a selection of an 8- 38, 37, 36, 4, 3, 2, 1, 40, 6, 5, 4, 3, 2, bit byte from the 1,048,576 available. 35, 34, 3, 2 13, 37 1, 48, 17, 16 31 C 45 dq15/ input/ data i/o: msb of data when byte# = high. address input: lsb (a - 1) output of address input when byte# = low during read or write operation. 15, 17, 19, 25, 26, 27, 29, 31, 33, dq0C input/ data i/os: data output pins during any read operation or 21, 24, 26, 28, 32, 33, 35, 38, 40, dq7 output data input pins during a write. these pins are used to input 28, 30 34, 35 42, 44 commands to the cel. 16, 18, 20, C 30, 32, 34, dq8C input/ data i/os: data output pins during any read operation or 22, 25, 27, 36, 39, 41, dq14 output data input pins during a write when byte# = high. these 29 43 pins are high-z when byte# is low. 11113v pp supply write/erase supply voltage: from a write or erase confirm until completion of the write or erase, v pp must be at v pph 1 (3.3v) or v pph 2 (5v). v pp = dont care during all other operations. 23 30, 31 37 v cc supply power supply: +3.3v 0.3v. 13, 32 23, 39 27, 46 v ss supply ground. C 29, 38 9, 10, 15 nc C no connect: these pins may be driven or left unconnected.
5 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory note: 1. l = v il (low), h = v ih (high), x = v il or v ih (dont care). 2. v pph = v pph 1 = 3.3v or v pph 2 = 5v. 3. operation must be preceded by erase setup command. 4. operation must be preceded by write setup command. 5. the read array command must be issued before reading the array after writing or erasing. 6. when wp# = v ih , rp# may be at v ih or v hh . 7. v hh = 12v. 8. v id = 12v; may also be read by issuing the identify device command. 9. a1Ca8, a10Ca18 = v il . 10. value reflects dq8Cdq15. truth table (mt28f800b3) 1 function rp# ce# oe# we# wp# byte# a0 a9 v pp dq0Cdq7 dq8Cdq14 dq15/a - 1 standby h h x x x x x x x high-z high-z high-z reset l x x x x x x x x high-z high-z high-z read read (word mode) h l l h x h x x x data-out data-out data-out read (byte mode) h l l h x l x x x data-out high-z a-1 output disable h l h h x x x x x high-z high-z high-z write/erase (except boot block) 2 erase setup h l h l x x x x x 20h x x erase confirm 3 hl hlxxxxv pph d0h x x write setup h l h l x x x x x 10h/40h x x write (word mode) 4 hl hlxhxxv pph data-in data-in data-in write (byte mode) 4 hl hlxlxxv pph data-in x a-1 read array 5 hl hlxxxxx ffh x x write/erase (boot block) 2, 7 erase setup h l h l x x x x x 20h x x erase confirm 3 v hh lhlxxxxv pph d0h x x erase confirm 3, 6 hl hlhxxxv pph d0h x x write setup h l h l x x x x x 10h/40h x x write (word mode) 4 v hh lhlxhxxv pph data-in data-in data-in write (word mode) 4, 6 hl hlhhxxv pph data-in data-in data-in write (byte mode) 4 v hh lhlxlxxv pph data-in x a-1 write (byte mode) 4, 6 hl hlhlxxv pph data-in x a-1 read array 5 hl hlxxxxx ffh x x device identification 8, 9 manufacturer compatibility h l l h x h l v id x 89h 00h C (word mode) 10 manufacturer compatibility h l l h x l l v id x 89h high-z x (byte mode) device (word mode, top boot) 10 hl lhxhhv id x 9ch 88h C device (byte mode, top boot) h l l h x l h v id x 9ch high-z x device (word mode, bottom boot) 10 hl lhxhhv id x 9dh 88h C device (byte mode, bottom boot) h l l h x l h v id x 9dh high-z x
6 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory note: 1. l = v il , h = v ih , x = v il or v ih . 2. v pph = v pph 1 = 3.3v or v pph 2 = 5v. 3. operation must be preceded by erase setup command. 4. operation must be preceded by write setup command. 5. the read array command must be issued before reading the array after writing or erasing. 6. when wp# = v ih , rp# may be at v ih or v hh . 7. v hh = 12v. 8. v id = 12v; may also be read by issuing the identify device command. 9. a1Ca8, a10Ca19 = v il . truth table (mt28f008b3) 1 function rp# ce# oe# we# wp# a0 a9 v pp dq0Cdq7 standby h h xxxxxx high-z reset l x xxxxxx high-z read read h l l h x x x x data-out output disable h l h h x x x x high-z write/erase (except boot block) 2 erase setup h l h l x x x x 20h erase confirm 3 hlhlxxxv pph d0h write setup h l h l x x x x 10h/40h write 4 hlhlxxxv pph data-in read array 5 hlhlxxxx ffh write/erase (boot block) 2, 7 erase setup h l h l x x x x 20h erase confirm 3 v hh lhlxxxv pph d0h erase confirm 3, 6 hlhlhxxv pph d0h write setup h l h l x x x x 10h/40h write 4 v hh lhlxxxv pph data-in write 4, 6 hlhlhxxv pph data-in read array 5 hlhlxxxx ffh device identification 8, 9 manufacturer compatibility h l l h x l v id x 89h device (top boot) h l l h x h v id x 98h device (bottom boot) h l l h x h v id x 99h
7 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory functional description the mt28f800b3 and mt28f008b3 flash devices in- corporate a number of features ideally suited for system firmware. the memory array is segmented into indi- vidual erase blocks. each block may be erased without affecting data stored in other blocks. these memory blocks are read, written and erased with commands to the command execution logic (cel). the cel controls the operation of the internal state machine (ism), which completely controls all write, block erase and verify operations. the ism protects each memory location from over-erasure and optimizes each memory location for maximum data retention. in addition, the ism greatly simplifies the control necessary for writing the device in- system or in an external programmer. the functional description provides detailed infor- mation on the operation of the mt28f800b3 and mt28f008b3 and is organized into these sections: ? overview ? memory architecture ? output (read) operations ? input operations ? command set ? ism status register ? command execution ? error handling ? write/erase cycle endurance ? power usage ? power-up overview smart 3 technology (b3) smart 3 operation allows maximum flexibility for in- system read, write and erase operations. write and erase operations may be executed with a v pp voltage of 3.3v or 5v. due to process technology advances, 5v v pp is optimal for application and production programming. eleven independently erasable memory blocks the mt28f800b3 and mt28f008b3 are organized into eleven independently erasable memory blocks that al- low portions of the memory to be erased without affect- ing the rest of the memory data. a special boot block is hardware-protected against inadvertent erasure or writ- ing by requiring either a super-voltage on the rp# pin or driving the wp# pin high. (the wp# pin does not apply to the sop package.) one of these two conditions must exist along with the v pp voltage (3.3v or 5v) on the v pp pin before a write or erase is performed on the boot block. the remaining blocks require that only the v pp voltage be present on the v pp pin before writing or erasing. hardware-protected boot block this block of the memory array can be erased or written only when the rp# pin is taken to v hh or when the wp# pin is brought high. (the wp# pin does not apply to the sop package.) this provides additional security for the core firmware during in-system firmware updates should an unintentional power fluctuation or system reset occur. the mt28f800b3 and mt28f008b3 are avail- able with the boot block starting at the bottom of the address space (b suffix) and the top of the address space (t suffix). selectable bus size (mt28f800b3) the mt28f800b3 allows selection of an 8-bit (1 meg x 8) or 16-bit (512k x 16) data bus for reading and writing the memory. the byte# pin is used to select the bus width. in the x16 configuration, control data is read or written only on the lower eight bits (dq0Cdq7). data written to the memory array utilizes all active data pins for the selected configuration. when the x8 configuration is selected, data is written in byte form; when the x16 configuration is selected, data is written in word form. internal state machine (ism) block erase and byte/word write timing are simplified with an ism that controls all erase and write algorithms in the memory array. the ism ensures protec- tion against overerasure and optimizes write margin to each cell. during write operations, the ism automatically in- crements and monitors write attempts, verifies write margin on each memory cell and updates the ism status register. when block erase is performed, the ism au- tomatically overwrites the entire addressed block (elimi- nates overerasure), increments and monitors erase at- tempts, and sets bits in the ism status register. ism status register the ism status register enables an external processor to monitor the status of the ism during write and erase operations. two bits of the 8-bit status register are set and cleared entirely by the ism. these bits indicate whether the ism is busy with an erase or write task and when an erase has been suspended. additional error informa- tion is set in three other bits: v pp status, write status and erase status. command execution logic (cel) the cel receives and interprets commands to the device. these commands control the operation of the ism and the read path (i.e., memory array, id register or status register). commands may be issued to the cel
8 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory figure 1 memory address maps top boot mt28f008b3/800b3xx-xxt bottom boot mt28f008b3/800b3xx-xxb while the ism is active. however, there are restrictions on what commands are allowed in this condition. see the command execution section for more detail. deep power-down mode to allow for maximum power conservation, the mt28f800b3 and mt28f008b3 feature a very low cur- rent, deep power-down mode. to enter this mode, the rp# pin is taken to v ss 0.2v. in this mode, the current draw is a maximum of 8a at 3.3v v cc . entering deep power-down also clears the status register and sets the ism to the read array mode. memory architecture the mt28f800b3 and mt28f008b3 memory array architecture is designed to allow sections to be erased without disturbing the rest of the array. the array is divided into eleven addressable blocks that vary in size and are independently erasable. when blocks rather than the entire array are erased, total device endurance is enhanced, as is system flexibility. only the erase func- tion is block-oriented. all read and write operations are done on a random-access basis. the boot block is protected from unintentional erase or write with a hardware protection circuit which re- quires that a super-voltage be applied to rp# or that the wp# pin be driven high before erasure is commenced. the boot block is intended for the core firmware required for basic system functionality. the remaining ten blocks do not require that either of these two conditions be met before write or erase operations. boot block the hardware-protected boot block provides extra security for the most sensitive portions of the firmware. this 16kb block may only be erased or written when the rp# pin is at the specified boot block unlock voltage (v hh ) of 12v or when the wp# pin is high. during a write or erase of the boot block, the rp# pin must be held at v hh or the wp# pin held high until the write or erase is completed. (the wp# pin does not apply to the sop package.) the v pp pin must be at v pph (3.3v or 5v) when the boot block is written to or erased. fffffh fc000h fbfffh fa000h f9fffh f8000h f7fffh e0000h dffffh c0000h bffffh a0000h 9ffffh 80000h 7ffffh 60000h 5ffffh 40000h 3ffffh 20000h 1ffffh 00000h 16kb boot block 8kb parameter block 8kb parameter block 96kb main block 128kb main block 128kb main block 128kb main block 128kb main block 128kb main block 128kb main block 128kb main block byte address 7ffffh 7e000h 7dfffh 7d000h 7cfffh 7c000h 7bfffh 70000h 6ffffh 60000h 5ffffh 50000h 4ffffh 40000h 3ffffh 30000h 2ffffh 20000h 1ffffh 10000h 0ffffh 00000h word address 128kb main block 128kb main block 128kb main block 128kb main block 128kb main block 128kb main block 128kb main block 96kb main block 8kb parameter block 8kb parameter block 16kb boot block byte address fffffh e0000h dffffh c0000h bffffh a0000h 9ffffh 80000h 7ffffh 60000h 5ffffh 40000h 3ffffh 20000h 1ffffh 08000h 07fffh 06000h 05fffh 04000h 03fffh 00000h 7ffffh 70000h 6ffffh 60000h 5ffffh 50000h 4ffffh 40000h 3ffffh 30000h 2ffffh 20000h 1ffffh 10000h 0ffffh 04000h 03fffh 03000h 02fffh 02000h 01fffh 00000h word address
9 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory status register performing a read of the status register requires the same input sequencing as a read of the array except that the address inputs are dont care. the status register contents are always output on dq0C dq7, regardless of the condition of byte# on the mt28f800b3. dq8Cdq15 are low when byte# is high, and dq8Cdq14 are high-z when byte# is low. data from the status register is latched on the falling edge of oe# or ce#, whichever occurs last. if the con- tents of the status register change during a read of the status register, either oe# or ce# may be toggled while the other is held low to update the output. following a write or erase, the device automati- cally enters the status register read mode. in addition, a read during a write or erase produces the status register contents on dq0Cdq7. when the device is in the erase suspend mode, a read operation produces the status register contents until another command is is- sued. in certain other modes, read status register may be given to return to the status register read mode. all commands and their operations are described in the command set and command execution sections. identification register a read of the two 8-bit device identification registers requires the same input sequencing as a read of the array. we# must be high, and oe# and ce# must be low. however, id register data is output only on dq0C dq7, regardless of the condition of byte# on the mt28f800b3. a0 is used to decode between the two bytes of the device id register; all other address inputs are dont care. when a0 is low, the manufacturer com- patibility id is output, and when a0 is high, the device id is output. dq8Cdq15 are high-z when byte# is low. when byte# is high, dq8Cdq15 are 00h when the manufacturer compatibility id is read and 88h when the device id is read. to get to the identification register read mode, read identification may be issued while the device is in certain other modes. in addition, the identification regis- ter read mode can be reached by applying a super-volt- age (v id ) to the a9 pin. using this method, the id register can be read while the device is in any mode. when a9 is returned to v il or v ih , the device returns to the previous mode. input operations the dq pins are used either to input data to the array or to input a command to the cel. a command input issues an 8-bit command to the cel to control the mode of operation of the device. a write is used to input data to the memory array. the following section de- the mt28f800b3 and mt28f008b3 are available in two configurations and top or bottom boot block. the top boot block version supports processors of the x86 variety. the bottom boot block version is intended for 680x0 and risc applications. figure 1 illustrates the memory ad- dress maps associated with these two versions. parameter blocks the two 8kb parameter blocks store less sensitive and more frequently changing system parameters and also may store configuration or diagnostic coding. these blocks are enabled for erasure when the v pp pin is at v pph . no super-voltage unlock or wp# control is required. main memory blocks the eight remaining blocks are general-purpose memory blocks and do not require a super-voltage on rp# or wp# control to be erased or written. these blocks are intended for code storage, rom-resident applica- tions or operating systems that require in-system update capability. output (read) operations the mt28f800b3 and mt28f008b3 feature three dif- ferent types of reads. depending on the current mode of the device, a read operation produces data from the memory array, status register or device identification register. in each of these three cases, the we#, ce# and oe# inputs are controlled in a similar manner. moving between modes to perform a specific read is described in the command execution section. memory array to read the memory array, we# must be high, and oe# and ce# must be low. valid data is output on the dq pins when these conditions have been met, and a valid address is given. valid data remains on the dq pins until the address changes, or until oe# or ce# goes high, whichever occurs first. the dq pins continue to output new data after each address transition as long as oe# and ce# remain low. the mt28f800b3 features selectable bus widths. when the memory array is accessed as a 512k x 16, byte# is high, and data is output on dq0Cdq15. to access the memory array as a 1 meg x 8, byte# must be low, dq8C dq14 must be high-z, and all data must be output on dq0Cdq7. the dq15/(a - 1) pin becomes the lowest order address input so that 1,048,576 locations can be read. after power-up or reset, the device is automatically in the array read mode. all commands and their opera- tions are covered in the command set and command execution sections.
10 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory scribes both types of inputs. more information describ- ing how to use the two types of inputs to write or erase the device is provided in the command execution sec- tion. commands to perform a command input, oe# must be high, and ce# and we# must be low. addresses are dont care but must be held stable, except during an erase confirm (described in a later section). the 8-bit com- mand is input on dq0Cdq7, while dq8Cdq15 are dont care on the mt28f800b3. the command is latched on the rising edge of ce# (ce#-controlled) or we# (we#- controlled), whichever occurs first. the condition of byte# on the mt28f800b3 has no effect on a com- mand input. memory array a write to the memory array sets the desired bits to logic 0s but cannot change a given bit to a logic 1 from a logic 0. setting any bits to a logic 1 requires that the entire block be erased. to perform a write, oe# must be high, ce# and we# must be low, and v pp must be set to v pph 1 or v pph 2 . writing to the boot block also requires that the rp# pin be at v hh or wp# be high. a0Ca18 (a19) pro- vide the address to be written, while the data to be written to the array is input on the dq pins. the data and addresses are latched on the rising edge of ce# (ce#-controlled) or we# (we#-controlled), whichever occurs first. a write must be preceded by a write setup command. details on how to input data to the array are described in the write sequence section. selectable bus sizing applies to writes as it does to reads on the mt28f800b3. when byte# is low (byte mode), data is input on dq0Cdq7, dq8Cdq14 are high- z, and dq15 becomes the lowest order address input. when byte# is high (word mode), data is input on dq0C dq15. command set to simplify writing of the memory blocks, the mt28f800b3 and mt28f008b3 incorporate an ism that controls all internal algorithms for writing and erasing the floating gate memory cells. an 8-bit command set is used to control the device. details on how to sequence commands are provided in the command execution section. table 1 lists the valid commands. table 1 command set command hex code description reserved 00h this command and all unlisted commands are invalid and should not be called. these commands are reserved to allow for future feature enhancements. read array ffh must be issued after any other command cycle before the array can be read. it is not necessary to issue this command after power-up or reset. identify device 90h allows the device and manufacturer compatibility id to be read. a0 is used to decode between the manufacturer compatibility id (a0 = low) and device id (a0 = high). read status register 70h allows the status register to be read. please refer to table 2 for more information on the status register bits. clear status register 50h clears status register bits 3-5, which cannot be cleared by the ism. erase setup 20h the first command given in the two-cycle erase sequence. the erase is not completed unless followed by erase confirm. erase confirm/resume d0h the second command given in the two-cycle erase sequence. must follow an erase setup command to be valid. also used during an erase suspend to resume the erase. write setup 40h or the first command given in the two-cycle write sequence. the write 10h data and address are given in the following cycle to complete the write. erase suspend b0h requests a halt of the erase and puts the device into the erase suspend mode. when the device is in this mode, only read status register, read array and erase resume commands may be executed.
11 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory ism status register the 8-bit ism status register (see table 2) is polled to check for write or erase completion or any related errors. during or following a write, erase or erase suspend, a read operation outputs the status register contents on dq0Cdq7 without prior command. while the status register contents are read, the outputs are not be updated if there is a change in the ism status unless oe# or ce# is toggled. if the device is not in the write, erase, erase suspend or status register read mode, read status register (70h) can be issued to view the status register contents. all of the defined bits are set by the ism, but only the ism and erase suspend status bits are reset by the ism. the erase, write and v pp status bits must be cleared using clear status register. if the v pp status bit (sr3) is set, the cel does not allow further write or erase operations until the status register is cleared. this enables the user to choose when to poll and clear the status register. for example, the host system may perform multiple byte write operations before check- ing the status register instead of checking after each individual write. asserting the rp# signal or power- ing down the device also clears the status register. status bit # status register bit description sr7 ism status (isms) the isms bit displays the active status of the state machine during 1 = ready write or block erase operations. the controlling logic polls this 0 = busy bit to determine when the erase and write status bits are valid. sr6 erase suspend status (ess) issuing an erase suspend places the ism in the suspend mode 1 = erase suspended and sets this and the isms bit to 1. the ess bit remains 1 0 = erase in progress/completed until an erase resume is issued. sr5 erase status (es) es is set to 1 after the maximum number of erase cycles is 1 = block erase error executed by the ism without a successful verify. es is only cleared 0 = successful block erase by a clear status register command or after a reset. sr4 write status (ws) ws is set to 1 after the maximum number of write cycles is 1 = word/byte write error executed by the ism without a successful verify. ws is only cleared 0 = successful word/byte write by a clear status register command or after a reset. sr3 v pp status (v pp s) v pp s detects the presence of a v pp voltage. it does not monitor v pp 1 = no v pp voltage detected continuously, nor does it indicate a valid v pp voltage. the v pp pin 0 = v pp present is sampled for 3.3v or 5v after write or erase confirm is given. v pp s must be cleared by clear status register or by a reset. sr0-2 reserved reserved for future use. table 2 status register bit definitions isms ess es ws v pp sr 765432C0
12 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory command execution commands are issued to bring the device into differ- ent operational modes. each mode allows specific opera- tions to be performed. several modes require a sequence of commands to be written before they are reached. the following section describes the properties of each mode, and table 3 lists all command sequences required to perform the desired operation. read array the array read mode is the initial state of the device upon power-up and after a reset. if the device is in any other mode, read array (ffh) must be given to return to the array read mode. unlike the write setup com- mand (40h), read array does not need to be given before each individual read access. identify device identify device (90h) may be written to the cel to enter the identify device mode. while the device is in this mode, any read produces the device identification when a0 is high and the manufacturer compatibility identifi- cation when a0 is low. the device remains in this mode until another command is given. table 3 command sequences bus first second cycles cycle cycle commands reqd operation address data operation address data notes read array 1 write x ffh 1 identify device 3 write x 90h read ia id 2, 3 read status register 2 write x 70h read x srd 4 clear status register 1 write x 50h erase setup/confirm 2 write x 20h write ba d0h 5, 6 erase suspend/resume 2 write x b0h write x d0h write setup/write 2 write x 40h write wa wd 6, 7 alternate word/byte 2 write x 10h write wa wd 6, 7 write note: 1. must follow write or erase confirm commands to the cel in order to enable flash array read cycles. 2. ia = identify address: 00h for manufacturer compatibility id; 01h for device id. 3. id = identify data. 4. srd = status register data. 5. ba = block address (a12Ca19). 6. addresses are dont care in first cycle but must be held stable. 7. wa = address to be written; wd = data to be written to wa. write sequence two consecutive cycles are needed to input data to the array. write setup (40h or 10h) is given in the first cycle. the next cycle is the write, during which the write address and data are issued and v pp is brought to v pph . writing to the boot block also requires that the rp# pin be brought to v hh or the wp# pin be brought high at the same time v pp is brought to v pph . the ism now begins to write the word or byte. v pp must be held at v pph until the write is completed (sr7 = 1). while the ism executes the write, the ism status bit (sr7) is at 0, and the device does not respond to any commands. any read operation produces the status register contents on dq0Cdq7. when the ism status bit (sr7) is set to a logic 1, the write has been completed, and the device goes into the status register read mode until another command is given. after the ism has initiated the write, it cannot be aborted except by a reset or by powering down the part. doing either during a write corrupts the data being written. if only the write setup command has been given, the write may be nullified by performing a null write. to execute a null write, ffh must be written
13 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory when byte# is low, or ffffh must be written when byte# is high. when the ism status bit (sr7) has been set, the device is in the status register read mode until another command is issued. erase sequence executing an erase sequence sets all bits within a block to logic 1. the command sequence necessary to execute an erase is similar to that of a write. to pro- vide added security against accidental block erasure, two consecutive command cycles are required to initiate an erase of a block. in the first cycle, addresses are dont care, and erase setup (20h) is given. in the second cycle, v pp must be brought to v pph , an address within the block to be erased must be issued, and erase confirm (d0h) must be given. if a command other than erase confirm is given, the write and erase status bits (sr4 and sr5) are set, and the device is in the status register read mode. after the erase confirm (d0h) is issued, the ism starts the erase of the addressed block. any read operation outputs the status register contents on dq0C dq7. v pp must be held at v pph until the erase is com- pleted (sr7 = 1). when the erase is completed, the device is in the status register read mode until another command is issued. erasing the boot block also requires that either the rp# pin be set to v hh or the wp# pin be held high at the same time v pp is set to v pph . erase suspension the only command that may be issued while an erase is in progress is erase suspend. this com- mand enables other commands to be executed while pausing the erase in progress. when the device has reached the erase suspend mode, the erase suspend status bit (sr6) and ism status bit (sr7) are set. the device may now be given a read array, erase re- sume or read status register command. after read array has been issued, any location not within the block being erased may be read. if erase resume is issued before sr6 has been set, the device immedi- ately proceeds with the erase in progress. error handling after the ism status bit (sr7) has been set, the v pp (sr3), write (sr4) and erase (sr5) status bits may be checked. if one or a combination of these three bits has been set, an error has occurred. the ism cannot reset these three bits. to clear these bits, clear status reg- ister (50h) must be given. if the v pp status bit (sr3) is set, further write or erase operations cannot resume until the status register is cleared. table 4 lists the combina- tion of errors. table 4 status register error code description 1 status bits sr5 sr4 sr3 error description 0 0 0 no errors 001v pp voltage error 0 1 0 write error 0 1 1 write error, v pp voltage not valid at time of write 1 0 0 erase error 1 0 1 erase error, v pp voltage not valid at time of erase confirm 1 1 0 command sequencing error or write/erase error 1 1 1 command sequencing error, v pp voltage error, with write and erase errors note: 1. sr3-sr5 must be cleared using clear status register.
14 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory write/erase cycle endurance the mt28f800b3 and mt28f008b3 are designed and fabricated to meet advanced firmware storage require- ments. to ensure this level of reliability, v pp must be at 3.3v 0.3v or 5v 10% during write or erase cycles. due to process technology advances, 5v v pp is optimal for application and production programming. power usage the mt28f800b3 and mt28f008b3 offer several power-saving features that may be utilized in the array read mode to conserve power. deep power-down mode is enabled by bringing rp# low. current draw (i cc ) in this mode is a maximum of 8a at 3.3v v cc . when ce# is high, the device enters standby mode. in this mode, maximum i cc current is 100a at 3.3v v cc . if ce# is brought high during a write or erase, the ism contin- ues to operate, and the device consumes the respective active power until the write or erase is completed. power-up the likelihood of unwanted write or erase opera- tions is minimized because two consecutive cycles are required to execute either operation. however, to reset the ism and to provide additional protection while v cc is ramping, one of the following conditions must be met: ? rp# must be held low until v cc is at valid functional level; or ? ce# or we# may be held high and rp# must be toggled from v cc -gnd-v cc . after a power-up or reset, the status register is reset, and the device enters the array read mode. figure 2 power-up/reset timing diagram valid valid v cc (3.3v) data address t note 1 rp# rwh t aa note: 1. v cc must be within the valid operating range before rp# goes high. undefined
15 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory yes no write 40h or 10h v pp = 3.3v or 5v start write word or byte address/data status register read sr7 = 1? complete status check (optional) write complete 3 2 no start (write completed) yes sr4 = 0? sr3 = 0? no yes byte/word write error 5 write successful v error pp 4, 5 complete write status-check sequence self-timed write sequence (word or byte write) 1 note: 1. sequence may be repeated for additional byte or word writes. 2. complete status check is not required. however, if sr3 = 1, further writes are inhibited until the status register is cleared. 3. device will be in status register read mode. to return to the array read mode, the ffh command must be issued. 4. if sr3 is set during a write or block erase attempt, clear status register must be issued before further write or erase operations are allowed by the cel. 5. status register bits 3-5 must be cleared using clear status register.
16 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory no start (erase completed) yes sr4, 5 = 1? sr3 = 0? yes yes command sequence error sr5 = 0? no no 6 v error pp block erase error 5, 6 6 erase successful yes no v pp = 3.3v or 5v complete status check (optional) erase complete no yes suspend erase? status register read sr7 = 1? write 20h start write d0h, block address suspend sequence erase resumed erase busy 3 4 2 self-timed block erase sequence 1 complete block erase status-check sequence note: 1. sequence may be repeated to erase additional blocks. 2. complete status check is not required. however, if sr3 = 1, further erases are inhibited until the status register is cleared. 3. to return to the array read mode, the ffh command must be issued. 4. refer to the erase suspend flowchart for more information. 5. if sr3 is set during a write or block erase attempt, clear status register must be issued before further write or erase operations are allowed by the cel. 6. status register bits 3-5 must be cleared using clear status register.
17 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory erase suspend/resume sequence no write b0h (erase suspend) start (erase in progress) write ffh (read array) status register read yes sr6 = 1? sr7 = 1? no yes no yes done reading? write d0h (erase resume) resume erase erase completed v pp = 3.3v or 5v
18 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory absolute maximum ratings* voltage on v cc supply relative to v ss ..................................... -0.5v to +4v** input voltage relative to v ss .................... -0.5v to +4v** v pp voltage relative to v ss ........................ -0.5v to +5.5v ? rp# or a9 pin voltage relative to v ss ................................ -0.5v to +12.6v ?? temperature under bias .......................... -10oc to +80oc storage temperature (plastic) ............... -55oc to +125oc power dissipation ......................................................... 1w *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. **v cc , input and i/o pins may transition to -2v for <20ns and v cc + 2v for <20ns. ? voltage may pulse to -2v for <20ns and 7v for <20ns. ?? voltage may pulse to -2v for <20ns and 14v for <20ns. electrical characteristics and recommended dc read operating conditions commercial temperature (0oc t a +70oc) and extended temperature (-40oc t a +85oc) parameter/condition symbol min max units notes 3.3v supply voltage v cc 3 3.6 v 1 input high (logic 1) voltage, all inputs v ih 2.4 v cc + 0.5 v 1 input low (logic 0) voltage, all inputs v il -0.5 0.8 v 1 device identification voltage, a9 v id 10 12.6 v 1 v pp supply voltage v pp -0.5 5.5 v 1 dc operating characteristics commercial temperature (0oc t a +70oc) and extended temperature (-40oc t a +85oc) parameter/condition symbol min max units notes output voltage levels v oh v cc - 0.2 C v output high voltage (i oh = -100a) 1 output low voltage (i ol = 2ma) v ol C 0.45 v input leakage current any input (0v v in v cc ); i l -1 1 a all other pins not under test = 0v input leakage current: a9 input i id C 500 a (10v a9 12v = v id ) input leakage current: rp# input i hh C 500 a (10v rp# 12v = v hh ) output leakage current i oz -10 10 a (d out is disabled; 0v v out v cc ) note: 1. all voltages referenced to v ss .
19 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory read and standby current drain 1 commercial temperature (0oc t a +70oc) and extended temperature (-40oc t a +85oc) parameter/condition symbol max units notes read current: word-wide (ce# 0.2v; oe# ? v cc - 0.2v; f = 5 mhz; i cc 1 15 ma 2, 3 other inputs 0.2v or ? v cc - 0.2v; rp# ? v cc - 0.2v) read current: byte-wide (ce# 0.2v; oe# ? v cc - 0.2v; f = 5 mhz; i cc 2 15 ma 2, 3 other inputs 0.2v or ? v cc - 0.2v; rp# = v cc - 0.2v) standby current: ttl input levels v cc power supply standby current i cc 3 2ma (ce# = rp# = v ih ; other inputs = v il or v ih ) standby current: cmos input levels v cc power supply standby current i cc 4 100 a (ce# = rp# = v cc - 0.2v) deep power-down current: v cc supply i cc 6 8a (rp# = v ss 0.2v) standby or read current: v pp supply i pp 1 15 a (v pp 5.5v) deep power-down current: v pp supply i pp 2 5a (rp# = v ss 0.2v) capacitance (t a = 25oc; f = 1 mhz) parameter/condition symbol max units notes input capacitance c i 9pf output capacitance c o 12 pf note: 1. v cc = max v cc during i cc tests. 2. i cc is dependent on cycle rates. 3. i cc is dependent on output loading. specified values are obtained with the outputs open.
20 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory read timing parameters electrical characteristics and recommended ac operating conditions 1 commercial temperature (0oc t a +70oc) and extended temperature (-40oc t a +85oc); v cc = +3.3v 0.3v ac characteristics -9/-9 et parameter symbol min max units notes read cycle time t rc 90 ns access time from ce# t ace 90 ns 2 access time from oe# t aoe 40 ns 2 access time from address t aa 90 ns rp# high to output valid delay t rwh 1,000 ns oe# or ce# high to output in high-z t od 25 ns output hold time from oe#, ce# or address change t oh 0 ns rp# low pulse width t rp 150 ns note: 1. measurements tested under ac test conditions. 2. oe# may be delayed by t ace minus t aoe after ce# falls before t ace is affected. ac test conditions input pulse levels ...................................................... 0v to 3v input rise and fall times ................................................ <10ns input timing reference level ........................................... 1.5v output timing reference level ........................................ 1.5v output load ................................... 1 ttl gate and c l = 50pf
21 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory word-wide read cycle 1 valid data valid address ce# a0Ca18/(a19) oe# dq0Cdq15 t rc t ace t aoe t od t oh t aa we# rp# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t rwh dont care undefined note: 1. byte# = high (mt28f800b3 only). -9/-9 et symbol min max units timing parameters commercial temperature (0oc t a +70oc) extended temperature (-40oc t a +85oc) -9/-9 et symbol min max units t rc 90 ns t ace 90 ns t aoe 40 ns t aa 90 ns t rwh 1,000 ns t od 25 ns t oh 0 ns
22 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory byte-wide read cycle 1 valid data valid address ce# a0Ca18/(a19) oe# dq0Cdq7 dont care undefined t rc t ace t aoe t od t oh t aa we# rp# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t rwh dq8Cdq14 v ih v il high-z note: 1. byte# = low (mt28f800b3 only). -9/-9 et symbol min max units timing parameters commercial temperature (0oc t a +70oc) extended temperature (-40oc t a +85oc) -9/-9 et symbol min max units t rc 90 ns t ace 90 ns t aoe 40 ns t aa 90 ns t rwh 1,000 ns t od 25 ns t oh 0 ns
23 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory write/erase current drain 4 commercial temperature (0oc t a +70oc) and extended temperature (-40oc - t a - +85oc); v cc = +3.3v 0.3v 3.3v v pp 5v v pp parameter/condition symbol max max units notes word write current: v cc supply i cc 7 20 20 ma 5 word write current: v pp supply i pp 3 20 20 ma 5 byte write current: v cc supply i cc 8 20 20 ma 6 byte write current: v pp supply i pp 4 20 20 ma 6 erase current: v cc supply i cc 9 25 25 ma erase current: v pp supply i pp 5 25 30 ma erase suspend current: v cc supply i cc 10 810ma7 (erase suspended) erase suspend current: v pp supply i pp 6 200 200 a (erase suspended) recommended dc write/erase conditions 1 commercial temperature (0oc t a +70oc) and extended temperature (-40oc t a +85oc); v cc = +3.3v 0.3v parameter/condition symbol min max units notes v pp write/erase lockout voltage v pplk C 1.5 v 2 v pp voltage during write/erase operation v pph 1 3.0 3.6 v 3 v pp voltage during write/erase operation v pph 2 4.5 5.5 v boot block unlock voltage v hh 10 12.6 v v cc write/erase lockout voltage v lko 2Cv note: 1. write operations are tested at v pp voltages equal to or less than the previous erase. 2. absolute write/erase protection when v pp v pplk . 3. when 3.3v v cc and v pp are used, v cc cannot exceed v pp by more than 500mv during write and erase operations. 4. all currents are in rms unless otherwise noted. 5. applies to mt28f800b3 only. 6. applies to mt28f008b3 and mt28f800b3 with byte# = low. 7. parameter is specified when device is not accessed. actual current draw will be i cc 10 plus read current if a read is executed while the device is in erase suspend mode.
24 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory speed-dependent write/erase ac timing characteristics and recommended ac operating conditions: we# (ce#)-controlled writes commercial temperature (0oc t a +70oc) and extended temperature (-40oc t a +85oc); v cc = +3.3v 0.3v ac characteristics -9/-9 et parameter symbol min max units notes write cycle time t wc 90 ns we# (ce#) high pulse width t wph ( t cph) 20 ns we# (ce#) pulse width t wp ( t cp) 50 ns address setup time to we# (ce#) high t as 50 ns address hold time from we# (ce#) high t ah 0 ns data setup time to we# (ce#) high t ds 50 ns data hold time from we# (ce#) high t dh 0 ns ce# (we#) setup time to we# (ce#) low t cs ( t ws) 0 ns ce# (we#) hold time from we# (ce#) high t ch ( t wh) 0 ns v pp setup time to we# (ce#) high t vps1 200 ns 1 v pp setup time to we# (ce#) high t vps2 100 ns 2 rp# high to we# (ce#) low delay t rs 1,000 ns rp# at v hh or wp# high setup time to we# (ce#) high t rhs 100 ns 3 write duration (word or byte write) t wed1 2 s 5 boot block erase duration t wed2 100 ms 5 parameter block erase duration t wed3 100 ms 5 main block erase duration t wed4 500 ms 5 we# (ce#) high to busy status (sr7 = 0) t wb 200 ns 4 v pp hold time from status data valid t vph 0 ns 5 rp# at v hh or wp# high hold time from status data valid t rhh 0 ns 3 boot block relock delay time t rel 100 ns 6 note: 1. measured with v pp = v pph 1 = 3.3v. 2. measured with v pp = v pph 2 = 5v. 3. rp# should be held at v hh or wp# held high until boot block write or erase is complete. 4. polling status register before t wb is met may falsely indicate write or erase completion. 5. write/erase times are measured to valid status register data (sr7 = 1). 6. t rel is required to relock boot block after write or erase to boot block. 7. typical values measured at t a = +25oc. 8. assumes no system overhead. 9. typical write times use checkerboard data pattern. word/byte write and erase duration characteristics 3.3v v pp 5v v pp parameter typ max typ max units notes boot/parameter block erase time 0.5 7 0.4 7 s 7 main block erase time 2.8 14 1.5 14 s 7 main block write time (byte mode) 1.5 C 1 C s 7, 8, 9 main block write time (word mode) 1.5 C 1 C s 7, 8, 9
25 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory write/erase cycle we#-controlled write/erase dont care t wc t wed1/2/3/4 t rs a in status (sr7=1) t ch t cs [unlock boot block] t rhs t as t ah t wp t wph t ds t dh cmd in t rhh cmd/ data-in cmd in write setup or erase setup input write or erase (block) address asserted, and write data or erase confirm issued write or erase executed, status register checked for completion command for next operation issued t dh t ds [unlock boot block] note 1 t as t ah status (sr7=0) t wb ce# a0Ca18/(a19) oe# dq0Cdq7/ dq0Cdq15 2 we# rp# 3 v ih v il v pp v ih v il v hh v pph1 v pph2 v ih v il v ih v il v ih v il v ih v il wp# 3 v ih v il v il t vps2 t vph t vps1 [5v v pp ] [3.3v v pp ] note: 1. address inputs are dont care but must be held stable. 2. if byte# is low, data and command are 8-bit. if byte# is high, data is 16-bit and command is 8-bit. 3. either rp# at v hh or wp# high unlocks the boot block. timing parameters commercial temperature (0oc t a +70oc) extended temperature (-40oc t a +85oc) -9/-9 et symbol min max units t wc 90 ns t wph 20 ns t wp 50 ns t as 50 ns t ah 0 ns t ds 50 ns t dh 0 ns t cs 0 ns t ch 0 ns t vps1 200 ns -9/-9 et symbol min max units t vps2 100 ns t rs 1,000 ns t rhs 100 ns t wed1 2 s t wed2 100 ms t wed3 100 ms t wed4 500 ms t wb 200 ns t vph 0 ns t rhh 0 ns
26 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory write/erase cycle ce#-controlled write/erase dont care t wc t wed1/2/3/4 t rs a in status (sr7=1) t wh t ws [unlock boot block] t vps2 t rhs t vph t as t ah t cp t cph t ds t dh cmd in t rhh cmd/ data-in cmd in write setup or erase setup input write or erase (block) address asserted, and write data or erase confirm issued write or erase executed, status register checked for completion command for next operation issued t dh t ds [unlock boot block] t vps1 note 1 t as t ah status (sr7=0) t wb we# a0Ca18/(a19) oe# dq0Cdq7/ dq0Cdq15 2 ce# rp# 3 v ih v il v pp v ih v il v hh v pph1 v pph2 v ih v il v ih v il v ih v il v ih v il wp# 3 v ih v il v il [5v v pp ] [3.3v v pp ] note: 1. address inputs are dont care but must be held stable. 2. if byte# is low, data and command are 8-bit. if byte# is high, data is 16-bit and command is 8-bit. 3. either rp# at v hh or wp# high unlocks the boot block. timing parameters commercial temperature (0oc t a +70oc) extended temperature (-40oc t a +85oc) -9/-9 et symbol min max units t wc 90 ns t cph 20 ns t cp 50 ns t as 50 ns t ah 0 ns t ds 50 ns t dh 0 ns t ws 0 ns t wh 0 ns t vps1 200 ns -9/-9 et symbol min max units t vps2 100 ns t rs 1,000 ns t rhs 100 ns t wed1 2 s t wed2 100 ms t wed3 100 ms t wed4 500 ms t wb 200 ns t vph 0 ns t rhh 0 ns
27 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory 40-pin plastic tsop i (10mm x 20mm) detail a .721 (18.31) .780 (19.80) .397 (10.08) .010 (0.25) .0197 (0.50) .010 (0.25) .007 (0.18) see detail a .795 (20.20) .727 (18.47) .006 (0.15) typ .005 (0.13) .391 (9.93) .024 (0.60) .016 (0.40) .008 (0.20) .004 (0.10) .002 (0.05) .0315 (0.80) .047 (1.20) max 40 1 20 21 .010 (0.25) plane gage pin #1 index note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01 per side.
28 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory 48-pin plastic tsop i (12mm x 20mm) .047 (1.20) max .005 (0.12) .007 (0.18) 24 .006 (0.15) .010 (0.25) see detail a .0197 (0.50) typ 1 .780 (19.80) .727 (18.47) .721 (18.31) .795 (20.20) .475 (12.07) .002 (0.05) detail a .016 (0.40) .024 (0.60) .0315 (0.80) .008 (0.20) .004 (0.10) .469 (11.91) 25 .010 (0.25) plane gage .010 (0.25) 48 pin #1 index note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01 per side.
29 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory 44-pin plastic sop 1 (600 mil) .016 (0.40) .010 (0.25) .066 (1.72) .020 (0.50) .015 (0.38) .007 (0.18) .005 (0.13) .004 (0.10) .643 (16.34) .620 (15.74) detail a pin #1 index (rotated 90 cw) see detail a gage plane .0315 (0.80) 1.113 (28.27) 1.107 (28.12) .010 (0.25) .499 (12.68) .493 (12.52) .030 (0.76) .106 (2.70) max .050 (1.27) typ note: 1. not recommended for new designs. 2. all dimensions in inches (millimeters) max or typical where noted. min 3. package width and length do not include mold protrusion; allowable mold protrusion is .01 per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 the micron logo and the m logo are trademarks of micron technology, inc.
30 8mb smart 3 boot block flash memory micron technology, inc., reserves the right to change products or specifications without notice. q10_3.p65 C rev. 3, pub. 10/01 ?2001, micron technology, inc. 8mb smart 3 boot block flash memory revision history rev. 3, pub. 10/01 ............................................................................................................. ...................................... 10/01 ? updated input capacitance spec ? changed access time to 90ns rev. 2 ............................................................................................................................... .......................................................... 3/01 ? changed to 0.18m process ? 12v v pp no longer supported ? 10v v hh 12v ?v oh v cc - 0.2v ? t rwh changed to 1s from 800ns ? t ah changed to 10ns from 0ns ? ac test output load c l changed to 50pf ? typical main block erase time changed to 1.5s from 1s ? typical main block write time (byte mode) changed to 1s from 0.5s ? typical main block write time (word mode) changed to 1s from 0.5s ? mt28f800b3 only available in wg and sg packages ? mt28f008b3 only available in vg package ? added 80ns access time for commercial and extended temperature ranges

▲Up To Search▲

Price & Availability of MT28F008B3WG-9B

	To Download MT28F008B3WG-9B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .